A capacitive element constituted of two-layered polysilicon (hereinafter, referred to as two-layered polysilicon capacitive element) is known as one of the capacitive elements of a semiconductor integrated circuit. The two-layered polysilicon capacitive element has a structure in which a silicon oxide film to be a dielectric is interposed between an upper electrode and a lower electrode.
A polysilicon film with its resistance lowered by doping impurities such as phosphorous or the like is used for the upper electrode and the lower electrode of the two-layered polysilicon capacitive element, in many cases. The silicon oxide film between the upper electrode and the lower electrode is formed by, in general, partially oxidizing the polysilicon film that is the lower electrode.
It is to be noted that, however, that the impurities remain in the silicon oxide film formed by thermally oxidizing directly the polysilicon film including the impurities such as phosphorous or the like. This poses disadvantages of degrading the breakdown voltage of the two-layered polysilicon capacitive element or causing the initial defect.
The above disadvantages are suppressed by reducing the concentration of impurities to be doped into the polysilicon film. If the concentration of impurities is reduced, however, another problem will be developed such that the depletion of the electrode cannot be suppressed and the applied electric field dependence of the capacitance value in the two-layered polysilicon capacitive element is increased.
As a conventional technique of the two-layered polysilicon capacitive element having a low applied electric field dependence of the capacitance value, “An insulating film manufacturing method of a semiconductor device” described in Patent Document 1 is known by way of example. In the semiconductor capacitance device described in Patent Document 1, the laminated structure of a thermal silicon oxide film and a silicon oxide film deposited by a low-pressure Chemical Vapor Deposition (CVD) process is used as a dielectric.
In addition, in the semiconductor capacitance device described in Patent Document 2, a silicon nitride film deposited by the CVD process is used as the dielectric. Furthermore, in the semiconductor device described in Patent Document 3, a silicon nitride film deposited by the low-pressure CVD process is formed as the dielectric. Moreover, in the semiconductor capacitance device described in Patent Document 4, non-doped amorphous silicon thermally oxidizing or thermally nitrided is used as the dielectric.